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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS
FEATURES:
* * * * * * *
IDTCV193 ADVANCE INFORMATION
Compliant with Intel CK505 Gen II spec One high precision PLL for CPU, SSC and N programming One high precision PLL for SRC, SSC and N programming One high precision PLL for SATA/PCI, and SSC One high precision PLL for 96MHz/48MHz Push-pull IOs for differential outputs Support spread spectrum modulation, -0.5 down spread and others * Support SMBus block read/write, byte read/write * Available in TSSOP package
KEY FEATURES
* Direct CPU and SRC clock frequency programming--write the Hex number into Byte [16:18], 1MHz stepping. * Linear and smooth transition for the CPU and SRC frequency programming. * SATA PLL source hardware select latch pin, PLL2 or PLL4. * Internal serial resistor hardware enable latch pin. * WOL 25MHz support.
OUTPUTS:
* * * * * * * *
2 - 0.7V differential CPU CLK pair 10 - 0.7V differential SRC CLK pair 1 - CPU_ITP/SRC differential clock pair 1 - SRC0/DOT96 differential clock pair 6 - PCI, 33.3MHz 1 - 48MHz 1 - REF 1 - SATA
KEY SPECIFICATIONS:
* CPU/SRC CLK cycle to cycle jitter < 85ps * PCI CLK cycle to cycle jitter < 500ps * All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II phase noise requirement. * SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal interpair skew = 0 ps
FUNCTIONAL BLOCK DIAGRAM
REF XTAL_IN PLL1 SSC N Programmable
XTAL Osc Amp
CPU[1:0] CPU Output Buffer Stop Logic
XTAL_OUT
CPU_ITP/SRC8
SDATA SCLK SM Bus Controller
PLL3 SSC PCI/SATA SRC CLK Output Buffer Stop Logic PLL4 SSC N Programmable
SRC1/25MHz/24.576MHz PCI[4:0], PCIF5 SATA/SRC2
CKPWRGD/PD# CPU_STOP# PCI_STOP# SRC5_EN ITP_EN CR_[H:A]# FSC,B,A SATA_SEL SR_ENABLE Control Logic Fixed PLL PLL2
SRC CLK Output Buffer Stop Logic
SRC[7:3], [11:9]
48MHz 48MHz/96MHz Output BUffer DOT96/SRC0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2005 Integrated Device Technology, Inc.
IDT CONFIDENTIAL
APRIL 8, 2009
DSC 7165
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0/ CR#_A Vdd_PCI PCI1/CR#_B *PCI2/SR_ENABLE **PCI3/SATA_SEL PCI4/ SRC5_EN PCIF5/ ITP_EN VSS_PCI Vdd_48 USB 48 / FS_A Vss_48 Vdd_IO SRCT0 / DOT96T SRCC0 / DOT96C VSS_IO Vdd_PLL3 SRCT1/25MHz0 SRCC1/25MHz1/24.576MHz Vss_PLL3 Vdd_PLL3_IO SRCT2/SATA SRCC2/SATA Vss_SRC SRCT3 / CR#_C SRCC3 / CR#_D Vdd_SRC_IO SRCT4 SRCC4 Vss_SRC SRCT9 SRCC9 SRCC11/CR#_G
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SCL SDA REF / FS_C / TestSel Vdd_REF Xtal_In Xtal_Out Vss_REF FS_B / TestMode CKPWRGD/PD# Vdd_CPU CPUT0 CPUC0 Vss_CPU CPUT1 CPUC1 Vdd_CPU_IO Sel_SRC1_25_24.576** SRCT8 /CPU_ ITPT SRCC8 /CPU_ ITPC Vdd_SRC_IO SRCT7/ CR#_F SRCC7/ CR#_E Vss_SRC SRCT6 SRCC6 Vdd_SRC PCI_Stop#/ SRCT5 CPU_Stop#/ SRCC5 Vdd_SRC_IO SRCC10 SRCT10 SRCT11/ CR#_H
* Internal 100k pull high ** Internal 100k pull low TSSOP TOP VIEW
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name PCI0/CR#_A VDD_PCI PCI1/CR#_B PCI2/SRC_ENABLE PCI3/SATA_SEL PCI4/SRC5_EN PCIF5/ITP_EN VSS_PCI VDD_48 USB 48/FS_A VSS_48 VDD_IO SRCT0/DOT96T SRCC0/DOT96C VSS_IO VDD_PLL3 SRCT1/25MHz SRCC1/25MHz1/24.576MHz VSS_PLL3 VDD_PLL3_IO SATAT/SRCT2 SATAC/SRCC2 VSS_SRC SRCT3/CR#_C SRCC3/CR#_D VDD_SRC_IO SRCT4 SRCC4 VSS_SRC SRCT9 SRCC9 SRCC11/CR#_G SRCT11/CR#_H SRCT10 SRCC10 VDD_SRC_IO CPU_Stop#/SRCC5 PCI_Stop#/SRCT5 VDD_SRC SRCC6 SRCT6 VSS_SRC Type I/O PWR I/O I/O OUT I/O I/O GND PWR I/O GND PWR OUT OUT GND PWR OUT OUT GND PWR OUT OUT GND I/O I/O PWR OUT OUT GND OUT OUT I/O I/O OUT OUT PWR I/O I/O PWR OUT OUT GND Description 33.33MHz. SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode. 3.3V 33.33MHz. SRC1, 4 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode.
Power on latch, high, internal 33 ohm resistor enabled. Low, disabled. Afterward 33.33MH
Power on Latch, high, SATA from PLL2. Low, SATA from PLL4 (as SRC clock). Afterward, 33.33MHz 33.33MHz. Pin 37, 38 mode selection. Power on latch, HIGH = SRC5, LOW = CPU and PCI Stop#. 33.33MHz. Pin 46, 47 mode selection. Power on latch, HIGH = CPU_ITP, LOW = SRC8. GND 3.3V 48MHz, frequency select, power on latch GND 1.05 ~ 3.3V Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0. Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0. GND 3.3V SRC or 25MHz, mode selected by pin 48, Sel_SRC1_25_24.576 SRC or 25Mhz or 24.576MHz, mode selected by pin 48, Sel_SRC1_25_24.576 GND 1.05 ~ 3.3V Differential output clock Differential output clock GND SRC clock. SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by SMBus control register. Default is SRC3. SRC clock. SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by SMBus control register. Default is SRC3. 1.05 ~ 3.3V Differential output clock Differential output clock GND Differential output clock Differential output clock SRC clock. SRC differential clock output enable, control SRC9, 0 = enable. Mode selected by SMBus control register. Default is SRC11. SRC clock. SRC differential clock output enable, control SRC10, 0 = enable. Mode selected by SMBus control register. Default is SRC11. Differential output clock Differential output clock 1.05 ~ 3.3V CPU stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN. PCI stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN. 3.3V Differential output clock Differential output clock GND
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name SRCC7/CR#_E SRCT7/CR#_F VDD_SRC_IO SRCC8/CPU_ ITPC SRCT8/CPU_ ITPT Sel_SRC1_25_24.576 VDD_CPU_IO CPUC1 CPUT1 VSS_CPU CPUC0 CPUT0 VDD_CPU CKPWRGD/PD# FS_B/TestMode VSS_REF XTAL_OUT XTAL_IN VDD_REF REF/FS_C/TestSel SDA SCL Type I/O I/O PWR OUT OUT OUT PWR OUT OUT GND OUT OUT PWR IN IN GND OUT IN PWR I/O I/O IN Description SRC clock. SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus control register. Default is SRC7. SRC clock. SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus control register. Default is SRC7. 1.05 ~ 3.3V SRC clock. CPU clock. Mode selected by pin7. SRC clock. CPU clock. Mode selected by pin7. Power on latch, Select pin 17, 18 Mode, see pin 48 Function Table. 1.05 ~ 3.3V Differential output clock Differential output clock GND Differential output clock Differential output clock 3.3V CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH. After, becomes power down, LOW active. Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table.q GND XTAL out XTAL in 3.3V 14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD assertion. SMBus data SMBus clock
TEST MODE SELECTION(1)
Test_Mode 1 0 CPU REF/N Hi-Z SRC REF/N Hi-Z
If TEST_SEL sampled above 2V at CKPWRGD active LOW
PCI/F REF/N Hi-Z REF REF Hi-Z DOT_96/DOT_SSC REF/N Hi-Z USB REF/N Hi-Z
NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with VIH_FS and VIL_FS thresholds.
FREQUENCY SELECTION
FSC, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 Reserve SRC[7:0] 100 100 100 100 100 100 100 100 PCI 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 4 USB 48 48 48 48 48 48 48 48 DOT 96 96 96 96 96 96 96 96 REF 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
IDT CONFIDENTIAL
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
SEL_SRC1_25_24.576 (PIN 48) VOLTAGE DECODING TABLE
state Low Mid High Min 0V 1.3V 2.4V Typ 0.55V 1.65V 2.75V Max 0.9V 2V VDD
SR_ENABLE TABLE
SR_ENABLE 0 1 (default) Need external 33 ohm serial resistor, Byte19 bit7 = 0 Enable 33 ohm internal serial resistor, Byte19 bit7 = 1
SEL_SRC1_25_24.576 FUNCTION TABLE
Sel_SRC1_25_24.576 (pin48 )
Low
CPU
PLL1
PCI
PLL4
Pin 17
25MHz, PLL3 (SS off) SRCT1 25MHz PLL2
Pin 18
25MHz PLL3 (SS off) SRCC1
SRC
48/96
PLL4 down PLL2, fixed
Mid High
PLL1 PLL1
PLL4 PLL4
PLL4 down PLL2, fixed
24.576MHz PLL4 down PLL2, fixed PLL3 (SS off)
SATA_SEL TABLE
SATA_SEL 0 1 SRC2/SATA PLL4 (SRC PLL, SSC) PLL2 (48/96 PLL)
DEVICE ID TABLE
ID3,ID2,ID1,ID0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CK505 56 pin TSSOP CK505 64 pin TSSOP 48 pin QFN 56 pin QFN 64 pin QFN 72 pin QFN 48 pin SSOP 56 pin SSOP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Comments CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 Derivative (non YC)
IO_VOUT [2:0] TABLE
000 001 010 011 100 101 110 111 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1V
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDA VDD TSTG TAMBIENT TCASE ESD Prot Description 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage GND - 0.5 Storage Temperature Ambient Operating Temperature Case Temperature Input ESD Protection Human Body Model
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
INDEX BLOCK READ PROTOCOL
Unit V V C C C V Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave
Min
Max 4.6 4.6 +150 +70 +115
Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit 30-37).
Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop
-65 0 2000
SM PROTOCOL INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop
Master Slave Master
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
N-PROGRAMMING PROCEDURE
* Byte 16 bit 3 has to be "1". This bit will decode the power on latched
. User writes the desired CPU frequency in HEX form into CPUN [8:0], * Byte 16, 17. * User writes the desired SRC frequency in HEX form into PN [7:0], Byte 18.
value of pins 4, 5 (see CFG table 1).
CONTROL REGISTERS BYTE 0
Bit 7 6 5 4 3 2 1 Output(s) Affected FSC FSB FSA iAMT_EN Reserved Reserved SRC2/SATA source Description/Function Latched FSC Latched FSB Latched FSA iAMT Mode 0 1 Type R R R RW RW RW RW Power On Latched Value Latched Value Latched Value HW M1 setting(1) 0 0 SATA_SEL latch
Legacy Mode
Enabled
PLL4 SMBUS control registers setting after the power down Power on default, With some exceptions
PLL2 Save register contents
0
PD_Restore
RW
1
NOTES: 1. Sticky 1, can only be reset by power off.
BYTE 1
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRC0_sel PLL1_SSC_DC PLL4_SSC_DC Reserved Reserved 25MHz_0 25MHz_1 PCI Description/Function Pin13/14 mode select SSC mode selection SSC mode selection 0 SRC0 Down spread Down spread 1 DOT96 Center spread Center spread Type RW RW RW RW RW RW RW RW Power On 0 1 0 0 0 1 1 1
PD# free run control PD# free run control
Disabled Disabled PLL2
Free run Free run PLL4
BYTE 2
Bit 7 6 5 4 3 2 1 0 Output(s) Affected REF USB_48 PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Description/Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 3
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRC11 SRC10 SRC9 SRC8/ITP SRC7 SRC6 SRC5 SRC4 Description/Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 4
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRC3 SATA/SRC2 SRC1 SRC0/DOT96 CPU1 CPU0 PLL1_SSC_ON PLL4_SSC_ON Description/Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SSC Enable SSC Enable 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 5
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CR#_A CR#_A control CR#_B CR#_B control CR#_C CR#_C control CR#_D CR#_D control Description/Function Pin1 mode selection CR#_A control selection Pin3 mode selection CR#_B control selection Pin24 mode selection CR#_C control selection Pin25 mode selection CR#_D control selection 0 PCI0 mode SRC0 PCI1mode SRC1(1) SRCT3 mode SRC0 SRCC3 mode SRC1 1 CR#_A mode SRC2 CR#_B mode SRC4 CR#_C mode SRC2 CR#_D mode SRC4 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0
NOTE: 1. Only when SRC1 is SRC Clock.
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 6(1)
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description/Function 0 1 CR#_E mode, Control SRC 6 CR#_F mode, Control SRC 8 CR#_G mode, Control SRC 9 CR#_H mode, Control SRC 10 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0 CR#_E Pin43 mode selection, control SRC6 SRCC7 mode CR#_F Pin44 mode selection, control SRC8 SRCT7 mode CR#_G Pin32 mode selection, control SRC9 SRCC11 mode CR#_H Pin33 mode selection, control SRC10 SRCT11 mode Reserved Reserved Reserved SRC_STP_CRTL If set, SRCs stop with PCI_STOP# Free running
Stoppable
NOTE: 1. STOP - CPUT and SRCT stay high, CPUC and SRCC stay low.
BYTE 7
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 0 1 Type Power On 0 0 0 0 0 1 0 1
BYTE 8
Bit 7 6 5 4 3 2 1 0 Output(s) affected Device_ID3 Device_ID2 Device_ID1 Device_ID0 Description/ Function See device ID table 0 1 Type R R R R RW RW RW RW Power On
0 0 1 1
Pin 17_SE_OE Pin 18_SE_OE
Output enable (Cannot be reset by PD Restore) Output enable (Can not be reset by PD Restore)
Disabled Disabled
Enabled Enabled
BYTE 9
Bit
7 6 5 4 3 2 1 0
Output(s) Affected
PCIF5 with PCI_STOP# Reserved REF Drive Strength
Description / Function
Free running Strength control Only valid when Byte9 bit3 is 1 Test Mode entry control
0
Free running
1
stoppable
Type
RW RW RW RW RW RW RW
Power On
0 1 0 0 1 0 1
1x 2x Hi-Z REF/N mode Normal operation Test mode, controlled by byte9 bit 4
IO_VOUT2 IO_VOUT1 IO_VOUT0
Programmable IO_VOUT voltage
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 10
Bit 7 6 5 4 3 2 1 0 Output(s) affected Description/ Function SRC5_EN_Strap PLL3 enable PLL2 enable SRC divider disable PCI divider disable CPU divider disable Controlled by CPU_STP# Controlled by CPU_STP# 0 1 Type R RW RW RW RW RW RW RW Power On The latch of SRC5_EN 1 1 1 1 1 1 1
PLL3 PLL2 SRC_DIV PCI_DIV CPU_DIV CPU1 Free run CPU0 Free run
PLL3 pwr dwn PLL2 pwr dwn disable disable disable Free run Free run
Pwr up Pwr up enable enable enable Controllable Controllable
BYTE 11 - RESERVED
Bit
7 6 5 4 3 2 1 0
Output(s) affected
Reserved Reserved Reserved Reserved CPU_ITP_AMT EN CPU1_AMT_EN PCI GEN II CPU_ITP_STOP EN
Description/ Function
0
1
Type
R R RW RW
Power On
0 1 0 1 1 1
M1 mode CLK enable at M1 mode Only if ITP_EN = 1 M1 mode CLK enable at M1 mode GEN II compliance Free run control
disable disable None GEN II Free run
enable enable GEN II Controlled
RW RW R RW
BYTE 12 - BYTE COUNT - DEFAULT 0x13H
BYTE 13
Bit 7 6 5 4 3 2 1 0 Output(s) Affected 48M REF PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Description / Function Strength Strength Strength Strength Strength Strength Strength Strength control control control control control control control control 0 1x 1x 1x 1x 1x 1x 1x 1x 1 2x 2x 2x 2x 2x 2x 2x 2x Type RW RW RW RW RW RW RW RW Power On 1 0 1 1 1 1 1 1
BYTE 14 RESERVED
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 15, WATCH DOG(1)
Bit
7 6 5 4 3 2 1 0
Output(s) Affected
Description / Function
0
1
Type
RW RW R R RW RW RW RW
Power On
0 0
Watch Dog Enable Watch Dog Alarm Enable Disabled Enabled Watch Dog Select Watch Dog Hard/Soft Alarm Select Hard Alarm Only Hard and Soft Alarm Watch Dog Hard Alarm Status Watch Dog Hard Alarm Status Normal Alarm Watch Dog Soft Alarm Status Watch Dog Soft Alarm Status Normal Alarm Watch Dog control Watch Dog Time Base Control 290ms base 1160ms base WD_1_ Timer 2 WatchDog_1_Alarm Timer WD_1_ Timer 1 Default is 7*290ms WD_1_ Timer 0
0 1 1 1
NOTE: 1. Hard Alarm switch to HW FS frequency.
BYTE 16
Bit Output(s) Affected Description / Function Set Byte15 bit7 = 1 after Power Down to enable the watch dog after the power down 0 1 Type Power On 7 6 5 WDEAPD Reserved Reserved Disabled Enabled RW RW RW 0 0 0
4 3 2 1 0
Test _scl N programming Enable Reserved Reserved CPUN8
On chip test mode enable
normal Disabled
SCLK=1, clk outputs = 1 SCLK=0, clk outputs=0 Enabled
RW RW RW RW RW
0 0 0 0 FS latch
BYTE 17 (PLL1)
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPUN7 CPUN6 CPUN5 CPUN4 CPUN3 CPUN2 CPUN1 CPUN0 Description / Function 0 1 Type RW RW RW RW RW RW RW RW FS latch Power On
CPU clock frequency = CPUN [8:0] (Hex)
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 18 (PLL4)
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PN 7 PN 6 PN 5 PN 4 PN 3 PN 2 PN 1 PN 0 Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On
SRC clock frequency = PNC [7:0] (Hex)
100MHz
BYTE 19 CLOCK SOURCE SELECTION, WRITTEN AFTER STOP BIT
Bit Output(s) Affected Description / Function 0 0 ohm (External resistor needed) 0.5% (p-p) 0.5% (p-p) 1 33 ohm (No external resistor needed) 0.45%(p-p) 0.45%(p-p) Type Power On SR_ENABLE latch 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Output serial resistor PLL1 SSC Reserved PLL4 SSC Reserved Reserved Reserved Reserved
spread % selection spread % selection
RW RW RW RW RW RW RW RW
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model GND - 0.5 -65 2000 150 MIN MAX 4.6 3.8 4.6 UNITS V V V V
Notes 1,7 1,7 1,7,8 1,7 1,7 1,7
C
V
ELECTRICAL CHARACTERISTICS - INPUT/SUPPLY/COMMON OUTPUT PARAMETERS
PARAMETER Ambient O perating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leak age Current Input Leak age Current O utput High Voltage O utput Low Voltage O utput High Voltage O utput Low Voltage Low Thres hold InputHigh Voltage (Tes t Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage O perating Supply Current SYMBO L Tambient VDDx xx VDDxx x_IO VIHS E VILS E I IN IINRE S VOHS E VOLS E VOHDIF VOLDIF VIH_FS _TE S T VIH_FS VIL_FS I DDOP 3.3 I DD_IO IDD_P D3.3 Power Down Current I DD_P DIO I DD_iA M T3.3 I DD_iA M T0.8 Fi L pin C IN Input Capac itance Spread Spec trum Modulation Frequency C OUT C INX fS S MOD Logic Inputs O utput pin capacitanc e X1 & X2 pins Triangular Modulation 30 1.5 CO NDITIO NS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = G ND Inputs with pull or pull down res istors VIN = VDD , VIN = G ND Single-ended outputs, IOH = -1mA Single-ended outputs , I OL = 1 mA Differential O utputs, IOH = TBD mA Differential O utputs, IOL = TBD mA 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% Full ac tive, C L =full load, IDD 3.3V Full activ e, C L =full load, IDD 3.3 3.3V supply, Power Down Mode 0.8V IO s upply, Power Down Mode 3.3V supply , iAMT Mode 0.8V IO s upply , iAMTMode VDD = 3.3 V 2 0.7 VS S - 0.3 0.7 MIN 0 3.135 1.05 2 VS S - 0.3 -5 -200 2.4 0.4 0.9 0.4 VDD + 0.3 1.5 0.35 200 70 5 0.1 80 10 15 7 5 6 TBD 33 MAX 70 3.465 3.3 VDD + 0.3 0.8 5 200 UNITS C V V V V uA uA V V V V V V V mA mA mA mA mA mA MHz nH pF pF pF k Hz Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1
iAMT Mode Current Input Frequenc y Pin Inductance
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - INPUT/COMMON PARAMETERS
PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB TDRSRC TDRPD TDRSRC TFALL TRISE CONDITIONS From VDD Power-Up or de-assertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS ms ns us ns ns ns Notes 1 1 1 1 1 1
AC ELECTRICAL CHARACTERISTICS - LOW POWER DIFFERENTIAL OUTPUTS
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL t SLR t FLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 150 250 MIN 2.5 2.5 MAX 8 8 20 1150 UNITS V/ns V/ns % mV mV mV mV mV % ps ps ps ps ps ps NOTES 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1,10
ELECTRICAL CHARACTERISTICS - PCICLK/PCICLK_F
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Intentional PCI-PCI delay Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL I OH I OL t SLR t FLR dt1 t skew t delay tjcyc-cyc V CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal/spread I OH = -1 mA IOL = 1 mA
OH @MIN
MIN -300 29.99100 29.49100 2.4
MAX 300 30.00900 30.15980 30.65980 0.4
UNITS NOTES ppm ns ns ns V V mA mA mA mA V/ns V/ns % ps ps ps 1,6 6 6 6 1 1 1 1 1 1 1 1 1 1 1,9 1
= 1.0 V
-33 -33 30 38 1 1 45 4 4 55 250 200 nominal 500
VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - USB48MHZ
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL I OH I OL t SLR t FLR dt1 tjcyc-cyc V CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal I OH = -1 mA IOL = 1 mA
OH @MIN = 1.0 V
MIN -100 20.83125 20.48130 2.4
MAX 100 20.83542 21.18540
UNITS NOTES ppm ns ns V 1,2 2 2 1 1 1 1 1 1 1 1 1 1
0.4 -29 -23 29 27 1 1 45 2 2 55 350
V mA mA mA mA V/ns V/ns % ps
VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V
ELECTRICAL CHARACTERISTICS - SMBUS INTERFACE
PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS @ I PULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 5.5 0.4 UNITS V V mA ns ns kHz Notes 1 1 1 1 1 1
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL I OH I OL t SLR t FLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal I OH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS ppm ns ns V V mA mA V/ns V/ns % ps Notes 1,2 2 2 1 1 1 1 1 1 1 1
Notes on Electrical Characteristics:
1 2 3 4 5
Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
6 7 8 9
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure SRC 3,4,6,7, are 0 ps nominal interpair skew
10
IDT CONFIDENTIAL
16
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PCI STOP FUNCTIONALITY
PCI_STOP# 1 0 SRC Normal High SRC# Normal Low PCI 33MHz Low
PCI_STOP# ASSERTION (TRANSITION FROM `1' TO `0')
tSU
PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - DE-ASSERTION (TRANSITION FROM '0' TO '1')
tSU tDRIVE_SRC PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
IDT CONFIDENTIAL
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IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CPU STOP FUNCTIONALITY
CPU_STOP# 1 0 CPU Normal High
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU# Normal Low
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a `0', CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP# tri-state bit corresponding to the CPU output of interest is programmed to a `1', CPU outputs will be tri-stated.
CPU_STOP# ASSERTION (TRANSITION FROM `1' TO `0')
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM `0' TO `1')
With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to `1', then the stopped CPU outputs will be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop 10nS > 200mV
IDT CONFIDENTIAL
18
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD# ASSERTION
PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
PD# DE-ASSERTION
tSTABLE <1.8mS PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
IDT CONFIDENTIAL
19
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
TSSOP PACKAGE DIMENSIONS
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
N
c
SYMBOL
L
E1 INDEX AREA
E
12
D
A A1 A2 b c D E E1 e L N aaa VARIATIONS
A2 A1
A
N 64
D mm. MIN 16.90 MAX 17.10 MIN .665
D (inch) MAX .673
-Ce
b SEA TING PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa C
ORDERING INFORMATION
IDTCV XXXX XXX XX Device Type Revision Package X T/R X Grade
Blank 8 PVG PAG C 193
Commercial Temperature Range (0C to +70C) Designation for tape and reel packaging Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green Revision Designator Programmable FlexPC Clock for P4 Processor
IDT CONFIDENTIAL
20
IDTCV193 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
REVISION HISTORY
August 15, 2007 August 21, 2007 December 07, 2007 April 08, 2008 April 24, 2008 June 24, 2008 October 20, 2008 April 8, 2009 Initial Release. Updated Pinout/Pin Description (pages 2-4). Added Sata_Sel Table (page 5). Updated SMBus (pages 7-12). Updated Byte 18 (pg. 12). Updated VDDxxx_IO supply voltage (pg. 13). Fixed Ordering Information (pg. 20). Added tape and reel ordering information (page 20) Corrected typo on pins 55 and 56 pin description (page 4) Updated Byte 1 (page 7). Updated Input/Supply Common Output Parameters table.
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support: pcclockhelp@idt.com
IDT CONFIDENTIAL
21

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